1) Field of the Invention
The present invention relates generally to the fabrication of capacitors and particularly to a method for fabricating a highly integrated semiconductor memory having a capacitor over bit-line (COB) structure and more particularly to a method to form a dynamic random access memory (DRAM) cell having a multiple pillar-shape capacitor.
2) Description of the Prior Art
The development of the semiconductor industry has always followed that of the Dynamic Random Access Memory (DRAM) technology in that DRAM development has led in the use of the highest density technology elements capable of being produced in manufacturable quantities. The development of DRAM's in the 4 Megabit density range began to depart from the twenty year tradition of two-dimensional DRAM designs by the appearance of three-dimensional DRAM cell structures, most notable by the use of trench capacitors. Proposed designs for DRAM cells in 16 MB, 64 MB and high density range have also included the use of multi-plate or stacked storage capacitor cell designs. Although the use of stacked cell technology has rendered the processing of DRAMs more complex such techniques continue to be used extensively.
The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors.
Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable to the three-dimensional stacked capacitor, and is more particularly suitable for an integrated memory cell which is 64 Mb or higher. Also, an improved stacked capacitor has recently been presented, where pillars or another inner cylinder is formed in the interior of another cylinder. Not only may both of the inner and outer surfaces of the cylinder be utilized as the effective capacitor area, but also the outer surface of the pillars or the inner cylinder formed in the interior of the cylinder. However, even more surface area and capacitance are required to achieve higher densities.
Recently, new technologies have been developed for increasing the effective surface area by modifying the surface morphology of the polysilicon storage electrode itself by engraving or by controlling the nucleation and growth condition of polysilicon. A hemispherical-grain (HSG) polysilicon layer can be deposited over a storage node to increase surface area and capacitance.
The following U.S. patents show related processes and capacitor structures: U.S. Pat. Nos. 5,342,800 to Jun., 5,304,828 to Kim et al., 5,358,888 to Ahn, and 5,302,540 to Ko et al. The following articles show related processes and capacitor structures: M. Sakao et al., "A Capacitor-Over-Bit-Line (COB) Cell With A Hemispherical Storage Node For 64 MB DRAMs," IEDM Tech Dig., Dec 1990, pp. 655-658; H. Watanabe et al., "A New Cylindrical Capacitor Using Hemispherical Grained Silicon (HSG-Si) For 256 Mb DRAMs," IEDM Tech Dig., Dec 1992, pp. 259-262; Sanggi Yu, et al, "The Honeycomb-Shape Capacitor Structure for ULSI DRAM", IEEE Electron Device Letters, Vol., 14, No 8, August 1993, p. 369-371; S. L. Wu et al., "Tunnel Oxide Prepared By Thermal Oxidation Of Thin Polysilicon Film On Silicon (TOPS)," IEEE Electron Device Lett., vol. 14, pp. 379-381, 1993; and Y. K. Jun et. al., "The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advance DRAM Applications", IEEE Electron Device Letters, vol. 13, no 8, August 1992, p. 430-432.
However, many of these methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Also, other process methods rely on etching to a predetermined etch depth which can be quite difficult to control in a manufacturing environment. Therefore, it is very desirable to develop processes that are as simple as possible and also have large process windows.
Recently, capacitor on bit line (COB) combined with the deposition of hemispherical grain silicon layer (HSG-Si) is proposed to increase the effective surface are of the storage node. See M. Sakao et al. But this method has limited capabilities to gain sufficient capacitance for advance (&gt;=256 Mb) DRAM applications. More recently, S. Yu et al. (see above) proposed a honeycomb-shaped capacitor structure to increase storage capacitance. However this method can be improved upon by reducing the leakage current. Therefore, a method is needed which can form multiple pillar-shaped capacitors with a high storage capacitance and a low leakage current.
There is also a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. There is also a challenge to develop a method to produce a capacitor with a minimum leakage current, a larger capacitance, a higher reliability and which is easy to manufacture.